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CY7C63411/12/13 CY7C63511/12/13
CY7C63411/12/13 CY7C63511/12/13 Low-Speed, High I/O, 1.5 Mbps USB Controller
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose * CA 95134 * 408-943-2600 February 1997 - Revised January 7, 1998
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TABLE OF CONTENTS
1.0 FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN ASSIGNMENTS ....................................................................................................................... 8 4.0 PROGRAMMING MODEL ............................................................................................................... 8 4.1 4.2 4.3 4.4 4.5 4.6 14-bit Program Counter (PC) ........................................................................................................... 8 8-bit Accumulator (A) ....................................................................................................................... 8 8-bit Index Register (X) .................................................................................................................... 8 8-bit Program Stack Pointer (PSP) .................................................................................................. 8 8-bit Data Stack Pointer (DSP) ........................................................................................................ 9 Address Modes ................................................................................................................................ 9
4.6.1 Data ........................................................................................................................................................ 9 4.6.2 Direct ...................................................................................................................................................... 9 4.6.3 Indexed ................................................................................................................................................... 9
5.0 INSTRUCTION SET SUMMARY ...................................................................................................10 6.0 6.1 6.2 6.3 MEMORY ORGANIZATION ..........................................................................................................11 Program Memory Organization ...................................................................................................... 11 Data Memory Organization ............................................................................................................ 12 I/O Register Summary ................................................................................................................... 13
7.0 CLOCKING ....................................................................................................................................14 8.0 RESET ...........................................................................................................................................14 8.1 Power-On Reset (POR) ................................................................................................................. 14 8.2 Watch Dog Reset (WDR) ............................................................................................................... 15 9.0 GENERAL PURPOSE I/O PORTS ...............................................................................................15 9.1 GPIO Interrupt Enable Ports ..........................................................................................................16 9.2 GPIO Configuration Port ................................................................................................................ 16 10.0 DAC PORT .................................................................................................................................. 17 10.1 DAC Port Interrupts .....................................................................................................................18 10.2 DAC Isink Registers .....................................................................................................................18 11.0 USB SERIAL INTERFACE ENGINE (SIE) .................................................................................18 11.1 USB Enumeration ........................................................................................................................ 19 11.2 PS/2 Operation ............................................................................................................................ 19 11.3 USB Port Status and Control .......................................................................................................19 12.0 USB DEVICE ............................................................................................................................... 20 12.1 USB Ports ....................................................................................................................................20 12.2 Device Endpoints (3) ................................................................................................................... 20 13.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 21 13.1 Timer (LSB) ................................................................................................................................. 21 13.2 Timer (MSB) ................................................................................................................................21 14.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 22
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TABLE OF CONTENTS (continued)
15.0 INTERRUPTS .............................................................................................................................. 22 15.1 Interrupt Vectors .......................................................................................................................... 23 15.2 Interrupt Latency .......................................................................................................................... 23
15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 USB Bus Reset Interrupt ....................................................................................................................23 Timer Interrupt .................................................................................................................................... 24 USB Endpoint Interrupts ..................................................................................................................... 24 DAC Interrupt ...................................................................................................................................... 24 GPIO Interrupt .................................................................................................................................... 24
16.0 TRUTH TABLES .........................................................................................................................24 17.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 27 18.0 DC CHARACTERISTICS ............................................................................................................ 28 19.0 SWITCHING CHARACTERISTICS ............................................................................................. 29 20.0 ORDERING INFORMATION .......................................................................................................31 21.0 PACKAGE DIAGRAMS ..............................................................................................................32
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LIST OF FIGURES Figure 6-1. Program Memory Space with Interrupt Vector Table ......................................................... 11 Figure 7-1. Clock Oscillator On-chip Circuit .......................................................................................... 14 Figure 8-1. Watch Dog Reset (WDR) ................................................................................................... 15 Figure 9-1. Block Diagram of a GPIO Line ........................................................................................... 15 Figure 9-2. Port 0 Data 0x00h (read/write) ........................................................................................... 16 Figure 9-3. Port 1 Data 0x01h (read/write) ........................................................................................... 16 Figure 9-4. Port 2 Data 0x02h (read/write) ........................................................................................... 16 Figure 9-5. Port 3 Data 0x03h (read/write) ........................................................................................... 16 Figure 9-6. Port 0 Interrupt Enable 0x04h (write only) .......................................................................... 16 Figure 9-7. Port 1 Interrupt Enable 0x05h (write only) .......................................................................... 16 Figure 9-8. Port 2 Interrupt Enable 0x06h (write only) .......................................................................... 16 Figure 9-9. Port 3 Interrupt Enable 0x07h (write only) .......................................................................... 16 Figure 9-10. GPIO Configuration Register 0x08h (write only) .............................................................. 17 Figure 10-1. Block Diagram of DAC Port .............................................................................................. 17 Figure 10-2. DAC Port Data 0x30h (read/write) .................................................................................... 18 Figure 10-3. DAC Port Interrupt Enable 0x31h (write only) .................................................................. 18 Figure 10-4. DAC Port Interrupt Polarity 0x32h (write only) ................................................................. 18 Figure 10-5. DAC Port Isink 0x38h to 0x3Fh (write only) ..................................................................... 18 Figure 11-1. USB Status and Control Register 0x1Fh .......................................................................... 19 Figure 12-1. USB Device Address Register 0x10h (read/write) ........................................................... 20 Figure 12-2. USB Device EPA0 Mode Register 0x12h (read/write) ..................................................... 20 Figure 12-3. USB Device Endpoint Mode Registers 0x14h, 0x16h (read/write) ................................... 20 Figure 12-4. USB Device Counter Registers 0x11h, 0x13h, 0x15h (read/write) .................................. 21 Figure 13-1. Timer Register 0x24h (read only) ..................................................................................... 21 Figure 13-2. Timer Register 0x25h (read only) ..................................................................................... 21 Figure 13-3. Timer Block Diagram ........................................................................................................ 21 Figure 14-1. Processor Status and Control Register 0xFFh ................................................................. 22 Figure 15-1. Global Interrupt Enable Register 0x20h (read/write) ........................................................ 22 Figure 15-2. USB End Point Interrupt Enable Register 0x21h (read/write) .......................................... 23 Figure 19-1. Clock Timing ..................................................................................................................... 29 Figure 19-2. USB Data Signal Timing ................................................................................................... 30 Figure 19-3. Receiver Jitter Tolerance ................................................................................................. 30 Figure 19-4. Differential to EOP Transition Skew and EOP Width ....................................................... 30 Figure 19-5. Differential Data Jitter ....................................................................................................... 31
LIST OF TABLES Table 6-1. I/O Register Summary ........................................................................................................ 13 Table 15-1. Interrupt Vector Assignments ........................................................................................... 23 Table 16-1. USB Register Mode Encoding .......................................................................................... 24 Table 16-2. Decode table forTable 16-3: "Details of Modes for Differing Traffic Conditions" .............. 25 Table 16-3. Details of Modes for Differing Traffic Conditions .............................................................. 26
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1.0 Features
* Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others. * USB Specification Compliance -- Conforms to USB Specification, Version 1.0 -- Conforms to USB HID Specification, Version 1.0 -- Supports 1 device address and 3 data endpoints -- Integrated USB transceiver * 8-bit RISC microcontroller -- Harvard architecture -- 6 MHz external ceramic resonator -- 12 MHz internal CPU clock * Internal memory -- 256 bytes of RAM -- 4 Kbytes of EPROM (CY7C63411, CY7C63511) -- 6 Kbytes of EPROM (CY7C63412, CY7C63512) -- 8 Kbytes of EPROM (CY7C63413, CY7C63513) * Interface can auto-configure to operate as PS2 or USB * I/O port -- 24 General Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (typical) -- Eight GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) which can drive LEDs -- Higher current drive is available by connecting multiple GPIO pins together to drive an common output -- Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs -- The CY7C63511/12/1 has an additional eight I/O pins on a DAC port which has programmable current sink outputs * * * * * * * * * * * -- Maskable interrupts on all I/O pins 12-bit free-running timer with one microsecond clock ticks Watchdog timer (WDT) Internal power-on reset (POR) Improved output drivers to reduce EMI Operating voltage from 4.0V to 5.5VDC Operating temperature from 0 to 70 degrees Celsius CY7C63411/12/13 available in 40-pin PDIP, 48-pin SSOP for production CY7C63411/12/13 available in 40-pin Windowed CerDIP, 48-pin Windowed SideBraze for program development CY7C63511/12/13 available in 48-pin SSOP packages for production CY7C63511/12/13 available in 48-pin Windowed SideBraze for program development Industry standard programmer support
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2.0 Functional Overview
The CY7C63411/12/13 and CY7C63511/12/13 are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C63411/12/13 features 32 general purpose I/O (GPIO) pins to support USB and other applications. The I/O pins are grouped into four ports (Port 0 to 3) where each port can be configured as inputs with internal pull-ups, open drain outputs, o r traditional CMOS outputs. 24 GPIO pins (Ports 0 to 2) are rated at 7 mA typical sink current. There are 8 GPIO pins (Port 3) which are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same "GPIO" interrupt vector. The CY7C63511/12/13 features an additional 8 I/O pins in the DAC port. Every DAC pin includes an integrated 14-Kohm pull-up resistor. When a "1" is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. When a "0" is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a "1" to the pin. The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits [7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I/O pin is individually programmable. The DAC port interrupts share a separate "DAC" interrupt vector. The Cypress microcontrollers use an external 6 MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6 and 12 MHz clocks that remain internal to the microcontroller. The CY7C63411/12/13 and CY7C63511/12/13 are offered with three EPROM options to maximize flexibility and minimize cost. The CY7C63411 and CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412 and CY7C63512 have 6 Kilobytes of EPROM. The CY7C63413 and CY7C63513 have 8 Kilobytes of EPROM. These parts include power-on reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The power-on reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watchdog timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watchdog reset. The microcontroller supports 8 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128 microsecond and 1.024 ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt (if enabled) when the bit toggles from low "0" to high "1". The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge ("0" to "1") or falling edge ("1" to "0"). The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 sec and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer twice: once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper 4 bits of the timer are latched into an internal register when the firmware reads the lower 8 bits. A read from the upper 4 bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper 4 bits happened to increment right after the lower 8 bits are read. The CY7C63411/12/13 and CY7C63511/12/13 include an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. Finally, the CY7C63411/12/13 and CY7C63511/12/13 support PS/2 operation. With appropriate firmware the D+ and D- USB pins can also be used as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.
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Logic Block Diagram
6 MHz ceramic resonator
Pin Configurations
CY7C63511/12/13 48-pin SSOP 48-pin SideBraze
D+ D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] DAC[7] DAC[5] P0[7] P0[5] P0[3] P0[1] DAC[3] DAC[1] VPP Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC Vss P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] DAC[6] DAC[4] P0[6] P0[4] P0[2] P0[0] DAC[2] DAC[0] XTALOUT XTALIN
CY7C63411/12/13 48-pin SSOP 48-pin SideBraze
D+ D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC NC P0[7] P0[5] P0[3] P0[1] NC NC VPP Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC Vss P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] NC NC P0[6] P0[4] P0[2] P0[0] NC NC XTALOUT XTALIN
OSC
12 MHz 6 MHz
12 MHz 8-bit CPU
USB Transceiver
D+ USB PS/2 D- PORT
EPROM 4/6/8 Kbyte 8-bit Bus
USB SIE
RAM 256 byte
Interrupt Controller
TOP VIEW
12-bit Timer
GPIO PORT 0
P0[0] P0[7]
CY7C63411/12/13 40-pin PDIP 40-pin CerDIP
D+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC VSS P3[6] P3[4] P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] P0[6] P0[4] P0[2] P0[0] XTALOUT XTALIN D- P3[7] P3[5] P3[3] P3[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P0[7] P0[5] P0[3] P0[1] VPP Vss
GPIO PORT 1
P1[0] P1[7]
GPIO PORT 2 Watchdog Timer
P2[0] P2[7]
GPIO PORT 3
P3[0] P3[7]
High Current Outputs
Power-on Reset
DAC PORT
DAC[0] DAC[7] CY7C63511/12/13 only
TOP VIEW
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3.0
Name D+, D- P0[7:0] I/O P1[7:0] I/O P2[7:0] I/O P3[7:0] I/O DAC[7:0] I/O
Pin Assignments
CY7C63411/12/13 I/O I/O 40-Pin 1,2 15,26,16,25, 17,24,18,23 11,30,12,29, 13,28,14,27 7,34,8,33, 9,32,10,31 3,38,4,37, 5,36,6,35 n/a 48-Pin 1,2 17,32,18,31, 19,30,20,29 11,38,12,37, 13,36,14,35 7,42,8,41, 9,40,10,39 3,46,4,45, 5,44,6,43 n/a CY7C63511/12/13 48-Pin 1,2 17,32,18,31, 19,30,20,29 11,38,12,37, 13,36,14,35 7,42,8,41, 9,40,10,39 3,46,4,45, 5,44,6,43 15,34,16,33, 21,28,22,27 Description USB differential data; PS/2 clock and data signals GPIO port 0 capable of sinking 7 mA (typical) GPIO Port 1 capable of sinking 7 mA (typical) GPIO Port 2 capable of sinking 7 mA (typical) GPIO Port 3 capable of sinking 12 mA (typical) DAC I/O Port with programmable current sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA typical. DAC[7:2] have a programmable sink current range of 0.2 to 1.0 mA typical. 6 MHz ceramic resonator or external clock input 6 MHz ceramic resonator Programming voltage supply, ground for normal operation Voltage supply Ground
XTALIN VPP VCC Vss
IN
21 22 19 40 20,39
25 26 23 48 24,47
25 26 23 48 24,47
XTALOUT OUT
4.0
4.1
Programming Model
14-bit Program Counter (PC)
The 14-bit program counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C634/5xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. This is typically a jump instruction to a reset handler that initializes the application. The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256 byte "page" of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution. The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction. Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.
4.2
8-bit Accumulator (A)
The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.
4.3
8-bit Index Register (X)
The index register "X" is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.
4.4
8-bit Program Stack Pointer (PSP)
During a reset, the program stack pointer (PSP) is set to zero. This means the program "stack" starts at RAM address 0x00 and "grows" upward from there. Note the program stack pointer is directly addressable under firmware control, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.
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During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program "stack" and increment the program stack pointer by two. The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to res tore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts. The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.
4.5
8-bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP. During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem. For USB applications, it is strongly recommended that the DSP is loaded after reset just below the USB DMA buffers.
4.6
Address Modes
The CY7C63411/12/13 and CY7C63511/12/13 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 4.6.1 Data
The "Data" address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xE8h: * MOV A,0E8h This instruction will require two bytes of code where the first byte identifies the "MOV A" instruction with a data operand as the second byte. The second byte of the instruction will be the constant "0xE8h". A constant may be referred to by name if a prior "EQU" statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above: * DSPINIT: EQU 0E8h * MOV A,DSPINIT 4.6.2 Direct
"Direct" address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h: * MOV A, [10h] In normal usage, variable names are assigned to variable addresses using "EQU" statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above: * buttons: EQU 10h * MOV A,[buttons] 4.6.3 Indexed
"Indexed" address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the "X" register. In normal usage, the constant will be the "base" address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed: * array: EQU 10h * MOV X,3 * MOV A,[x+array] This would have the effect of loading A with the fourth element of the SRAM "array" that begins at address 0x10h. The fourth element would be at address 0x13h.
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5.0 Instruction Set Summary
MNEMONIC HALT ADD A,expr ADD A,[expr] ADD A,[X+expr] ADC A,expr ADC A,[expr] ADC A,[X+expr] SUB A,expr SUB A,[expr] SUB A,[X+expr] SBB A,expr SBB A,[expr] SBB A,[X+expr] OR A,expr OR A,[expr] OR A,[X+expr] AND A,expr AND A,[expr] AND A,[X+expr] XOR A,expr XOR A,[expr] XOR A,[X+expr] CMP A,expr CMP A,[expr] CMP A,[X+expr] MOV A,expr MOV A,[expr] MOV A,[X+expr] MOV X,expr MOV X,[expr] data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct operand opcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 40 41 60 addr addr addr addr addr 50 - 5F 80-8F 90-9F A0-AF B0-BF 4 4 4 4 10 5 10 5 5 JC JNC JACC INDEX addr addr addr addr C0-CF D0-DF E0-EF F0-FF 5 5 7 14 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 5 7 8 4 5 6 4 5 cycles NOP INC A INC X INC [expr] INC [X+expr] DEC A DEC X DEC [expr] DEC [X+expr] IORD expr IOWR expr POP A POP X PUSH A PUSH X SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] CPL ASL ASR RLC RRC RET DI EI RETI direct index direct index direct index direct index index acc x direct index acc x direct index address address MNEMONIC operand opcode 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 70 72 73 4 4 4 7 8 4 4 7 8 5 5 4 4 5 5 4 4 5 6 7 8 7 8 7 8 6 4 4 4 4 4 8 4 4 8 cycles
reserved
XPAGE MOV A,X MOV X,A MOV PSP,A CALL JMP CALL JZ JNZ
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6.0
6.1
Memory Organization
Program Memory Organization
after reset 14-bit PC Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A Program execution begins here after a reset. USB Bus Reset interrupt vector 128 s timer interrupt vector 1.024 ms timer interrupt vector USB address A endpoint 0 interrupt vector USB address A endpoint 1 interrupt vector USB address A endpoint 2 interrupt vector Reserved Reserved Reserved DAC interrupt vector GPIO interrupt vector Reserved Program Memory begins here
0x0FFF
4 KB PROM ends here (CY7C63411,CY7C63511)
0x17FF
6 KB PROM ends here (CY7C63412, CY7C63512)
0x1FDF
(8K - 32 bytes) 8 KB PROM ends here (CY7C63413, CY7C63513)
Figure 6-1. Program Memory Space with Interrupt Vector Table
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6.2 Data Memory Organization
The CY7C63411/12/13 and CY7C63511/12/13 microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: after reset 8-bit PSP 8-bit DSP Address 0x00 user
Program Stack begins here and grows upward. Data Stack begins here and grows downward. The user determines the amount of memory required.
User Variables
0xE8 USB FIFO for Address A endpoint 2 0xF0 USB FIFO for Address A endpoint 1 0xF8 USB FIFO for Address A endpoint 0 Top of RAM Memory 0xFF
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6.3 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X. Table 6-1. I/O Register Summary Register Name Port 0 Data Port 1 Data Port 2 Data Port 3 Data Port 0 Interrupt Enable Port 1 Interrupt Enable Port 2 Interrupt Enable Port 3 Interrupt Enable GPIO Configuration USB Device Address A EP A0 Counter Register EP A0 Mode Register EP A1 Counter Register EP A1 Mode Register EP A2 Counter Register EP A2 Mode Register USB Status & Control Global Interrupt Enable Endpoint Interrupt Enable Timer (LSB) Timer (MSB) WDR Clear DAC Data DAC Interrupt Enable DAC Interrupt Polarity DAC Isink Processor Status & Control I/O Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x1F 0x20 0x21 0x24 0x25 0x26 0x30 0x31 0x32 0x38-0x3F 0xFF Read/Write R/W R/W R/W R/W W W W W R/W R/W R/W R/W R/W R/C R/W R/C R/W R/W R/W R R W R/W W W W R/W GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 Interrupt enable for pins in Port 0 Interrupt enable for pins in Port 1 Interrupt enable for pins in Port 2 Interrupt enable for pins in Port 3 GPIO Ports Configurations USB Device Address A USB Address A, Endpoint 0 counter register USB Address A, Endpoint 0 configuration register USB Address A, Endpoint 1 counter register USB Address A, Endpoint 1 configuration register USB address A, Endpoint 2 counter register USB address A, Endpoint 2 configuration register USB up-stream port traffic status and control register Global interrupt enable register USB endpoint interrupt enables Lower 8 bits of free-running timer (1 MHz) Upper 4 bits of free-running timer that are latched when the lower 8 bits are read. Watch Dog Reset clear DAC I/O Interrupt enable for each DAC pin. Interrupt polarity for each DAC pin One four bit sink current register for each DAC pin. Microprocessor status and control Function
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7.0 Clocking
Clock Distribution clk1x (to USB SIE) clk2x (to Microcontroller) Clock Doubler 30pF 30pF XTALOUT
XTALIN
Figure 7-1. Clock Oscillator On-chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator or an external oscillator can be connected to these pins to provide a reference frequency for the internal clock distribution and clock doubler. An external 6 MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Please note that grounding the XTALOUT pin is not permissible as the internal clock is effectively shorted to ground.
8.0
Reset
The USB Controller supports three types of resets. All registers are restored to their default states during a reset. The USB Device Addresses are set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) and Data Stack Pointer (DSP) are set to 0x00. For USB applications, the firmware should set the DSP below 0xE8h to avoid a memory conflict with RAM dedicated to USB FIFOs. The assembly instructions to do this are shown below: Mov A, E8h Swap A,dsp ; Move 0xE8 hex into Accumulator ; swap accumulator value into dsp register
The three reset types are: 1. Power-On Reset (POR) 2. Watch Dog Reset (WDR) 3. USB Bus Reset (non hardware reset) The occurrence of a reset is recorded in the Processor Status and Control Register located at I/O address 0xFF. Bits 4, 5, and 6 are used to record the occurrence of POR, USB Reset, and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. The microcontroller begins execution from ROM address 0x0000h after a POR or WDR reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. That means the reset handler in firmware should initialize the hardware and begin executing the "main" loop of code. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.
8.1
Power-On Reset (POR)
Power-On Reset (POR) occurs every time the VCC voltage to the device ramps from 0V to an internally defined trip voltage (Vrst), of approximately 1/2 full supply voltage. In addition to the normal reset initialization noted under "Reset," bit 4 (PORS) of t he Processor Status and Control Register is set to "1" to indicate to the firmware that a power on reset occurred. The POR event forces the GPIO ports into input mode (high impedance), and the state of Port 3 bit 7 is used to control how the part will respond after the POR releases. If Port 3 bit 7 is high (pulled to VCC) and the USB IO are at the idle state (DM high and DP low) the part will go into a semi-permanent power down/suspend mode, waiting for the USB IO to go to one of Bus Reset, K (resume) or SE0. If Port 3 bit 7 is still high when the part comes out of suspend, then a 128 us timer starts, delaying CPU operation until the ceramic resonator has stabilized. If Port 3 bit 7 was low (pulled to V SS) the part will start a 128 ms timer, delaying CPU operation until VCC has stabilized, then continuing to run as reset. Firmware should clear the POR Status (PORS) bit in register FFh before going into suspend as this status bit selects the 128 s or 128 ms start-up timer value as follows: IF Port 3 bit 7 is high then 128 s is always used; ELSE if PORS is high then 128 ms is used; ELSE 128 s is used.
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8.2 Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset initialization noted under "Reset," bit 6 of the Processor Status and Control Register is set to "1" to indicate to the firmware that a watchdog reset occurred.
8.192 ms to 14.336 ms
2.048 ms
At least 8.192 ms since last write to WDT
WDR goes high for 2.048 ms
Execution begins at Reset Vector 0X00
Figure 8-1. Watch Dog Reset (WDR) The Watch Dog Timer is a 2 bit timer clocked by a 4.096 ms clock (bit 11) from the free running timer. Writing any value to the write-only Watch Dog Clear I/O port (0x26h) will clear the Watch Dog Timer. In some applications, the Watch Dog Timer may be cleared in the 1.024 ms timer interrupt service routine. If the 1.024 ms timer interrupt service routine does not get executed for 8.192 ms or more, a Watch Dog Timer Reset will occur. A Watch Dog Timer Reset lasts for 2.048 ms after which the microcontroller begins execution at ROM address 0x0000h. The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The USB transmitter remains disabled until the MSB of the USB address register is set.
9.0
General Purpose I/O Ports
VCC
mode 2-bits Data Out Latch Q1 Control Q3
GPIO CFG
Internal Data Bus
7 K
Port Write Q2 ESD Internal Buffer
GPIO Pin
Control
Port Read Interrupt Enable
to Interrupt Controller
Figure 9-1. Block Diagram of a GPIO Line Ports 0 to 2 provide 24 GPIO pins that can be read or written. Each port (8 bits) can be configured as inputs with internal pul l-ups, open drain outputs, or traditional CMOS outputs. Please note an open drain output is also a high-impedance (no pull-up) input. All of the I/O pins within a given port have the same configuration. Ports 0 to 2 are considered low current drive with typical current sink capability of 7 mA. The internal pull-up resistors are typically 7 Kohms. Two factors govern the enabling and disabling of the internal pull-up resistors: the port configuration selected in the GPIO Configuration register and the state of the output data bit. If the GPIO Configuration selected is "Resistive" and the output data bit is "1," then the internal pull-up resistor is enabled for that GPIO pin. Otherwise, Q1 is turned off and the 7 Kohm pull-up is disabled. Q2 is "ON" to sink current whenever the output data bit is written as a "0." Q3
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provides "HIGH" source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a "1". Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to support traditional CMOS outputs with symmetric drive. P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]
Figure 9-2. Port 0 Data 0x00h (read/write) P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]
Figure 9-3. Port 1 Data 0x01h (read/write) P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0]
Figure 9-4. Port 2 Data 0x02h (read/write) P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0]
Figure 9-5. Port 3 Data 0x03h (read/write) Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. An open drain output is also a high-impedance input. Port 3 offers high current drive with a typical current sink capability of 12 mA. The internal pull-up resistors are typically 7 Kohms. During reset, all of the GPIO pins are set to output "1" (input) with the internal pull-up enabled. In this state, a "1" will always be read on that GPIO pin unless an external current sink drives the output to a "0" state. Writing a "0" to a GPIO pin enables the output current sink to ground (LOW) and disables the internal pull-up for that pin.
9.1
GPIO Interrupt Enable Ports
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a "1" to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]
Figure 9-6. Port 0 Interrupt Enable 0x04h (write only) P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]
Figure 9-7. Port 1 Interrupt Enable 0x05h (write only) P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0]
Figure 9-8. Port 2 Interrupt Enable 0x06h (write only) P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0]
Figure 9-9. Port 3 Interrupt Enable 0x07h (write only)
9.2
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In addition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge ("0" to "1") on an input pin causes an interrupt. With negative polarity, a falling edge ("1" to "0") on an input pin causes an interrupt. As shown in the table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port register provides two bits per port to program these features. The possible port configurations are:
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Port Configuration bits 11 10 10 01 00 Pin Interrupt Bit X 0 1 X X Driver Mode Resistive CMOS Output CMOS Input Open Drain Open Drain Interrupt Polarity disabled disabled + (default)
In "Resistive" mode, a 7 Kohm pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any pin that has been written as a "1." The resistor is disabled on any pin that has been written as a "0". An I/O pin will be driven high through a 7 Kohm pull-up resistor when a "1" has been written to the pin. Or the output pin will be driven LOW, with the pull-up disabled, when a "0" has been written to the pin. An I/O pin that has been written as a "1" can be used as an input pin with an integrated 7 Kohm pull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled. A port configured in CMOS mode has interrupt generation disabled, yet the interrupt mask bits serve to control port direction. If a port's associated Interrupt Mask bits are cleared, those port bits are strictly outputs. If the Interrupt Mask bits are set then those bits will be open drain inputs. As open drain inputs, if their data output values are `1' those port pins will be CMOS inputs (HIGH Z output). In "Open Drain" mode the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An I/O pin that has been written as a "1" can be used as either a high-impedance input or a three-state output. An I/O pin that has been written as a "0" will drive the output LOW. The interrupt polarity for an open drain GPIO port can be selected as either positive (rising edge) or negative (falling edge). During reset, all of the bits in the GPIO Configuration Register are written with "0". This selects the default configuration: Open Drain output, positive interrupt polarity for all GPIO ports. 7 Port 3 Config Bit 1 6 Port 3 Config Bit 0 5 Port 2 Config Bit 1 4 Port 2 Config Bit 0 3 Port 1 Config Bit 1 2 Port 1 Config Bit 0 1 Port 0 Config Bit 1 0 Port 0 Config Bit 0
Figure 9-10. GPIO Configuration Register 0x08h (write only)
10.0
DAC Port
VCC
Internal Data Bus Data Out Latch Q1
14 K DAC Write Isink Register Internal Buffer 4 bits Isink DAC
DAC I/O Pin
ESD
DAC Read Interrupt Enable Interrupt Polarity Interrupt Logic
to Interrupt Controller
Figure 10-1. Block Diagram of DAC Port
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The DAC port provides the CY7C63511/12/13 with 8 programmable current sink I/O pins. Writing a "1" to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14 Kohm resistor. When a "0" is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. A "0" output will cause the Isink DAC to sink current to drive the output LOW. The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register for that output pin. DAC[1:0] are the two high current outputs that are programmable from a minimum of 3.2 mA to a maximum of 16 mA (typical). DAC[7:2] are low current outputs that are programmable from a minimum of 0.2 mA to a maximum of 1.0 mA (typical). When a DAC I/O bit is written as a "1", the I/O pin is either an output pulled high through the 14 Kohm resistor or an input with an internal 14 Kohm pull-up resistor. All DAC port data bits are set to "1" during reset. Low current outputs 0.2 mA to 1.0 mA typical DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] Figure 10-2. DAC Port Data 0x30h (read/write) High current outputs 3.2 mA to 16 mA typical DAC[1] DAC[0]
10.1
DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature with an interrupt mask bit for each DAC I/O pin. Writing a "1" to a bit in this register enables interrupts from the corresponding bit position. Writing a "0" to a bit in the DAC Port Interrupt Enable register disables interrupts from the corresponding bit position. All of the DAC Port Interrupt Enable register bits are cleared to "0" during a reset. DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
Figure 10-3. DAC Port Interrupt Enable 0x31h (write only) As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register. Writing a "0" to a bit selects negative polarity (falling edge) that will cause an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. Writing a "1" to a bit in this register selects positive polarity (rising edge) that will cause an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are cleared during a reset. DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
Figure 10-4. DAC Port Interrupt Polarity 0x32h (write only)
10.2
DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The first Isink register (0x38h) controls the current for DAC[0], the second (0x39h) for DAC[1], and so on until the Isink register at 0x3Fh controls the current to DAC[7]. Reserved Isink[3] Isink Value Isink[2] Isink[1] Isink[0]
Figure 10-5. DAC Port Isink 0x38h to 0x3Fh (write only)
11.0
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB host. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: * Bit stuffing/unstuffing * Checksum generation/checking * ACK/NAK * Token type identification * Address checking Firmware is required to handle the rest of the USB interface with the following tasks: * Coordinate enumeration by responding to set-up packets
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* Fill and empty the FIFOs * Suspend/Resume coordination * Verify and select Data toggle values
11.1
USB Enumeration
The enumeration sequence is shown below: 1. The host computer sends a Setup packet followed by a Data packet to USB address 0 requesting the Device descriptor. 2. The USB Controller decodes the request and retrieves its Device descriptor from the program memory space. 3. The host computer performs a control read sequence and the USB Controller responds by sending the Device descriptor over the USB bus. 4. After receiving the descriptor, the host computer sends a Setup packet followed by a Data packet to address 0 assigning a new USB address to the device. 5. The USB Controller stores the new address in its USB Device Address Register after the no-data control sequence completes. 6. The host sends a request for the Device descriptor using the new USB address. 7. The USB Controller decodes the request and retrieves the Device descriptor from the program memory. 8. The host performs a control read sequence and the USB Controller responds by sending its Device descriptor over the USB bus. 9. The host generates control reads to the USB Controller to request the Configuration and Report descriptors. 10.The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB.
11.2
PS/2 Operation
PS/2 operation is possible with the CY7C634/5xx series through the use of firmware and several operating modes. The first enabling feature: 1. USB Bus reset on D+ and D- is an interrupt that can be disabled; 2. USB traffic can be disabled via bit7 of the USB register; 3. D+ and D- can be monitored and driven via firmware as independent port bits. Bits 5 and 4 of the Upstream Status and Control register are directly connected to the D+ and D- USB pins of the CY7C634/5xx. These pins constantly monitor the levels of these signals with CMOS input thresholds. Firmware can poll and decode these signal s as PS/2 clock and data. Bits [2:0] defaults to `000' at reset which allows the USB SIE to control output on D+ and D-. Firmware can override the SIE and directly control the state of these pins via these 3 control bits. Since PS/2 is an open drain signalling protocol, these modes allow all 4 PS/2 states to be generated on the D+ and D- pins
11.3
USB Port Status and Control
USB status and control is regulated by the USB Status and Control Register located at I/O address 0x1Fh as shown in Figure 11-1. This is a read/write register. All reserved bits must be written to zero. All bits in the register are cleared during reset. 7 Reserved 6 Reserved 5 R D+ 4 R D- 3 R/W Bus Activity 2 R/W Control Bit 2 1 R/W Control Bit 1 0 R/W Control Bit 0
Figure 11-1. USB Status and Control Register 0x1Fh The Bus Activity bit is a "sticky" bit that indicates if any non-idle USB event has occurred on the USB bus. The user firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a "0" to the Bus Activity bit clears it while writing a "1" preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024 ms timer interrupt service routine is normally used to check and clear the Bus Activity bit. The following table shows how the control bits are encoded for this register.
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Control Bits 000 001 010 011 100 101 110 111
Control action Not forcing (SIE controls driver) Force K (D+ high, D- low) Force J (D+ low, D- high) Force SE0 (D+ low, D- low) Force SE0 (D- low, D+ low) Force D- low, D+ HiZ Force D- HiZ, D+ low Force D- HiZ, D+ HiZ
12.0
USB Device
USB Device Address A includes three endpoints: EPA0, EPA1, and EPA2. End Point 0 (EPA0) allows the USB host to recognize, set-up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up) packets.
12.1
USB Ports
The USB Controller provides one USB device address with three endpoints. The USB Device Address Register contents are cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 12-1 shows the format of the USB Address Register. Device Address Enable Device Address Bit 6 Device Address Bit 5 Device Address Bit 4 Device Address Bit 3 Device Address Bit 2 Device Address Bit 1 Device Address Bit 0
Figure 12-1. USB Device Address Register 0x10h (read/write) Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the serial interface engine (SIE) will respond to USB traffic to this address. The Device Address in bits [6:0] must be set by firmware during the USB enumeration process to an address assigned by the USB host that does not equal zero. This register is cleared by a hardware reset or the USB bus reset.
12.2
Device Endpoints (3)
The USB controller communicates with the host using dedicated FIFOs, one per endpoint. Each endpoint FIFO is implemented as 8 bytes of dedicated SRAM. There are three endpoints defined for Device "A" that are labeled "EPA0," "EPA1," and EPA2." All USB devices are required to have an endpoint number 0 (EPA0) that is used to initialize and control the USB device. End Point 0 provides access to the device configuration information and allows generic USB status and control accesses. End Point 0 is bidirectional as the USB controller can both receive and transmit data. The endpoint mode registers are cleared during reset. The EPA0 endpoint mode register uses the format shown below: Endpoint 0 set-up Received Endpoint 0 In Received Endpoint 0 Out Received Acknowledge Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Figure 12-2. USB Device EPA0 Mode Register 0x12h (read/write) Bits[7:5] in the endpoint 0 mode registers (EPA0) are "sticky" status bits that are set by the SIE to report the type of token that was most recently received. The sticky bits must be cleared by firmware as part of the USB processing. The endpoint mode registers for EPA1 and EPA2 do not use bits [7:5] as shown below: Reserved Reserved Reserved Acknowledge Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Figure 12-3. USB Device Endpoint Mode Registers 0x14h, 0x16h (read/write) The `Acknowledge' bit is set whenever the SIE engages in a transaction that completes with an `ACK' packet.
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The `set-up' PID status (bit[7]) is forced high from the start of the data packet phase of the set-up transaction, until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until the CPU first does a IORD to this endpoint 0 mode register. Bits[6:0] of the endpoint 0 mode register are locked from CPU IOWR operations only if the SIE has updated one of these bits, which the SIE does only at the end of a packet transaction (set-up ... Data ... ACK, or Out ... Data ... ACK, or In ... Data ... ACK). The CPU can unlock these bits by doing a subsequent I/O read of this register. Firmware must do an IORD after an IOWR to an endpoint 0 register to verify that the contents have changed and that the SIE has not updated these values. While the `set-up' bit is set, the CPU cannot write to the DMA buffers at memory locations 0xE0 through 0xE7 and 0xF8 through 0xFF. This prevents an incoming set-up transaction from conflicting with a previous In data buffer filling operation by firmware. The mode bits (bits [3:0]) in an Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Section 16. The format of the endpoint Device counter registers is shown below: Data 0/1 Toggle Data Valid Reserved Reserved Byte count Bit 3 Byte count Bit 2 Byte count Bit 1 Byte count Bit 0
Figure 12-4. USB Device Counter Registers 0x11h, 0x13h, 0x15h (read/write) Bits 0 to 3 indicate the number of data bytes to be transmitted during an IN packet, valid values are 0 to 8 inclusive. Data Valid bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet's toggle state: 0 for DATA0, 1 for DATA1.
13.0
12-bit Free-running Timer
The 12-bit timer provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is actually reading the count stored in the temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.
13.1
Timer (LSB)
Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
Figure 13-1. Timer Register 0x24h (read only)
13.2
Timer (MSB)
Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8
Reserved
Figure 13-2. Timer Register 0x25h (read only)
1.024 ms interrupt 128 s interrupt
11
10
9
8
7
6
5
4
3
2
1
0
1 MHz clock
L3
L2
L1
L0
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0 To Timer Register
8
Figure 13-3. Timer Block Diagram
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14.0
7 R IRQ pending
Processor Status and Control Register
6 R/W Watch Dog Reset 5 R/W USB Bus Reset 4 R/W Power-on Reset 3 R/W Suspend, wait for interrupt 2 R Interrupt Mask 1 R/W Single Step 0 R/W Run
Figure 14-1. Processor Status and Control Register 0xFFh The "run" (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the end of the current instruction. The processor remains halted until a reset (power on or watchdog). Notice, when writing to the processor status and control register, the run bit should always be written as a "1". The "single step" (bit 1) is provided to support a hardware debugger. When single step is set, the processor will execute one instruction and halt (clear the run bit). This bit must be cleared for normal operation. The "Interrupt Mask" (bit 2) shows whether interrupts are enabled or disabled. The firmware has no direct control over this bit as writing a zero or one to this bit position will have no effect on interrupts. Instructions DI, EI, and RETI manipulate the internal hardware that controls the state of the interrupt mask bit in the Processor Status and Control Register. Writing a "1" to "Suspend, wait for interrupts" (bit 3) will halt the processor and cause the microcontroller to enter the "suspend" mode that significantly reduces power consumption. A pending interrupt or bus activity will cause the device to come out of suspend. After coming out of suspend, the device will resume firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR that attempts to put the part into suspend will be ignored if either bus activity or an interrupt is pending. The "Power-on Reset" (bit 4) is only set to "1" during a power on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power on condition or a watchdog timeout. PORS is used to determine suspend start-up timer value of 128us or 128ms. The "USB Bus Reset" (bit 5) will occur when a USB bus reset is received. The USB Bus Reset is a singled-ended zero (SE0) that lasts more than 8 microseconds. An SE0 is defined as the condition in which both the D+ line and the D- line are LOW at the same time. When the SIE detects this condition, the USB Bus Reset bit is set in the Processor Status and Control register and an USB Bus Reset interrupt is generated. Please note this is an interrupt to the microcontroller and does not actually reset the processor. The "Watch Dog Reset" (bit 6) is set during a reset initiated by the watchdog timer. This indicates the watchdog timer went for more than 8 ms between watch dog clears. The "IRQ pending" (bit 7) indicates one or more of the interrupts has been recognized as active. The interrupt acknowledge sequence should clear this bit until the next interrupt is detected. During power on reset, the Processor Status and Control Register is set to 00010001, which indicates a power-on-reset (bit 4 set) has occurred and no interrupts are pending (bit 7 clear), yet. During a watchdog reset, the Processor Status and Control Register is set to 01000001, which indicates a watchdog reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear), yet.
15.0
Interrupts
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a "1" to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts. 7 Reserved 6 Reserved 5 GPIO Interrupt Enable 4 R/W DAC Interrupt Enable 3 R/W Reserved 2 R/W 1.024 ms Interrupt Enable 1 R/W 128 sec Interrupt Enable 0 R/W USB Bus RST Interrupt Enable
Figure 15-1. Global Interrupt Enable Register 0x20h (read/write)
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7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 R/W EPA2 Interrupt Enable 1 R/W EPA1 Interrupt Enable 0 R/W EPA0 Interrupt Enable
Figure 15-2. USB End Point Interrupt Enable Register 0x21h (read/write) Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the hardware will first disable all interrupts by clearing the Interrupt Enable bit in the Processor Status and Control Register. Next, the interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited only by the available stack space. The Program Counter value as well as the Carry and Zero flags (CF, ZF) are automatically stored onto the Program Stack by the CALL instruction as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to restore the accumulator value. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed.
15.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 15-1. Although Reset is not an interrupt, per se, the first instruction executed after a reset is at PROM address 0x0000h - which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes. Table 15-1. Interrupt Vector Assignments Interrupt Vector Number not applicable 1 2 3 4 5 6 7 8 9 10 11 12 ROM Address 0x0000h 0x0002h 0x0004h 0x0006h 0x0008h 0x000Ah 0x000Ch 0x000Eh 0x0010h 0x0012h 0x0014h 0x0016h 0x0018h Function Execution after Reset begins here. USB Bus Reset interrupt 128 s timer interrupt 1.024 ms timer interrupt USB Address A Endpoint 0 interrupt USB Address A Endpoint 1 interrupt USB Address A Endpoint 2 interrupt Reserved Reserved Reserved DAC interrupt GPIO interrupt Reserved
15.2
Interrupt Latency
Interrupt latency can be calculated from the following equation: Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction) For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine will execute a min. of 16 clocks (1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is issued. Remember that the interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction. 15.2.1 USB Bus Reset Interrupt
The USB Bus Reset interrupt is asserted when a USB bus reset condition is detected. A USB bus reset is indicated by a single ended zero (SE0) on the upstream port for more than 8 microseconds. 23
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15.2.2 Timer Interrupt There are two timer interrupts: the 128 s interrupt and the 1.024 ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or the suspend request first. 15.2.3 USB Endpoint Interrupts
There are three USB endpoint interrupts, one per endpoint. The USB endpoints interrupt after the either the USB host or the USB controller sends a packet to the USB. 15.2.4 DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled.The interrupt polarity for each DAC I/O pin is programmable. A positive polarity is a rising edge input while a negative polarity is a falling edge input. All of the DAC pins share a single interrupt vector, which means the firmware will need to read the DAC port to determine which pin or pins caused an interrupt. Please note that if one DAC pin triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process. 15.2.5 GPIO Interrupt
Each of the 32 GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware will need to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. Please note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
16.0
Truth Tables
Mode Disable Encoding 0000 0001 Setup ignore accept 0010 0011 0100 0101 accept accept accept ignore 0110 0111 Nak Out Ack Out 1000 1001 1010 accept 1011 1100 1101 1110 accept 1111 TX cnt Check This mode is changed by SIE on issuance of ACK -->1110 ignore ignore accept NAK TX cnt NAK ignore ignore check An ACK from mode 1101 --> 1100 This mode is changed by SIE on issuance of ACK --> 1100 An ACK from mode 1111 --> 111 Ack In - Status Out TX 0 ACK This mode is changed by SIE on issuance of ACK --> 1010 ignore ignore accept ignore ignore TX 0 NAK ACK NAK accept ignore In ignore NAK stall stall ignore ignore TX 0 TX cnt Out ignore NAK check stall ignore always stall ignore Comments Ignore all USB traffic to this endpoint "Forced from Setup on Control endpoint, from modes other than 0000" For Control endpoints For Control endpoints For Control endpoints "(available to low speed devices, future USB spec enhancements)" In Only For Control Endpoints "(available to low speed devices, future USB spec enhancements)" An ACK from mode 1001 --> 1000 This mode is changed by SIE on issuance of ACK --> 1000 An ACK from mode 1011 --> 1010
Table 16-1. USB Register Mode Encoding
Nak In/Out Status Out Only Stall In/Out Ignore In/Out Isochronous Out Status In Only Isochronous In
Nak Out - Status In Ack Out - Status In Nak In Ack In Nak In - Status Out Ack In - Status Out
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The `In' column represents the SIE's response to the token type. A disabled endpoint will remain such until firmware changes it, and all endpoints reset to disabled. Any Setup packet to an enabled and accepting endpoint will be changed by the SIE to 0001 (NAKing).Any mode which indicates the acceptance of a Setup will acknowledge it. Most modes that control transactions involving an ending ACK will be changed by the SIE to a corresponding mode which NAKs follow on packets. A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as such. Also a non-Control endpoint can be made to act as a Control endpoint if it is placed in a non appropriate mode! A `check' on an Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG) of 1. Table 16-2. Decode table forTable 16-3: "Details of Modes for Differing Traffic Conditions" Properties of incoming packet Encoding Status bits What the SIE does to Mode bits PID Status bits
End Point Mode 3 2 1 0 Token Setup In Out The validity of the received data The quality status of the DMA buffer The number of received bytes Acknowledge phase completed count buffer dval DTOG DVAL COUNT Setup In Out ACK End Point Mode 3 2 1 0 Response Int
Interrupt?
Legend:
UC: unchanged x: don't care
TX: transmit RX: receive
TX0: transmit 0-length packet
available for Control endpoint only
The response of the SIE can be summarized as follows: (1) the SIE will only respond to valid transactions, and will ignore non-valid ones; (2) the SIE will generate IRQ when a valid transaction is completed or when the DMA buffer is corrupted (3) an incoming Data packet is valid if the count is <= 10 (CRC inclusive) and passes all error checking; (4) a Setup will be ignored by all non Control endpoints (in appropriate modes); (5) an In will be ignored by an Out configured endpoint and visa versa. The In and Out PID status is updated at the end of a transaction. The Setup PID status is updated at the beginning of the Data packet phase. The entire EndPoint 0 mode and the Count register are locked to CPU writes at the end of any transaction in which an ACK is transferred. These registers are only unlocked upon a CPU read of these registers, and only if that read happens after the transaction completes. This represents about a 1 s window to which to the CPU is locked from register writes to these USB registers. Normally the firmware does a register read at the beginning of the ISR to unlock and get the mode register informati on. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction!
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Table 16-3. Details of Modes for Differing Traffic Conditions
End Point Mode 3 2 1 0 token count buffer dval DTOG DVAL COUNT PID Setup In Out ACK Set End Point Mode 3 2 1 0 response int
Setup Packet (if accepting) SeeTable 16-1. SeeTable 16-1. See Table 16-1. Disabled 0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange ignore no Setup Setup Setup <= 10 > 10 x data junk junk valid x invalid updates updates updates 1 updates 0 updates updates updates 1 1 1 UC UC UC UC UC UC 1 UC UC 0 0 0 1 ACK ignore ignore yes yes yes
NoChange NoChange
Nak In/Out 0 0 0 0 0 0 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 1 UC UC UC NoChange NoChange NAK NAK yes yes
Ignore In/Out 0 0 1 1 0 0 0 0 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC UC UC UC UC UC NoChange NoChange ignore ignore no no
Stall In/Out 0 0 0 0 1 1 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 1 UC UC UC NoChange NoChange Stall Stall yes yes
Control Write Normal Out/premature status In 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 Out Out Out In <= 10 > 10 x x data junk junk UC valid x invalid x updates updates updates UC 1 updates 0 UC updates updates updates UC UC UC UC UC UC UC UC 1 1 1 1 UC 1 UC UC 1 1 0 1 0 ACK ignore ignore TX 0 yes yes yes yes
NoChange NoChange NoChange
NAK Out/premature status In 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 UC UC UC UC UC UC 1 NoChange NoChange NoChange NoChange NAK ignore ignore TX 0 yes no no yes
Status In/extra Out 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 UC UC UC UC UC UC 1 0 0 1 1 Stall ignore ignore TX 0 yes no no yes
NoChange NoChange NoChange
Control Read Normal In/premature status Out 1 1 1 1 1 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Out Out Out Out Out In token 2 2 !=2 > 10 x x count UC UC UC UC UC UC buffer valid valid valid x invalid x dval 1 0 updates UC UC UC DTOG 1 1 1 UC UC UC DVAL updates updates updates UC UC UC COUNT UC UC UC UC UC UC Setup UC UC UC UC UC 1 In 1 1 1 UC UC UC Out 1 UC UC UC UC 1 ACK NoChange 0 0 ACK yes yes yes no no yes int
0 1 1 Stall 0 1 1 Stall ignore ignore
NoChange NoChange 1 3
1 1 0 ACK (back) 2 1 0 response
Nak In/premature status Out 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Out Out Out Out Out In 2 2 !=2 > 10 x x UC UC UC UC UC UC valid valid valid x invalid x 1 0 updates UC UC UC 1 1 1 UC UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 1 1 1 UC UC UC 1 UC UC UC UC UC NoChange 0 0 ACK yes yes yes no no yes
0 1 1 Stall 0 1 1 Stall ignore ignore NAK
NoChange NoChange NoChange
Status Out/extra In 0 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
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Table 16-3. Details of Modes for Differing Traffic Conditions (continued)
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 Out Out Out Out In 2 !=2 > 10 x x UC UC UC UC UC valid valid x invalid x 0 updates UC UC UC 1 1 UC UC UC updates updates UC UC UC UC UC UC UC UC UC UC UC UC 1 1 1 UC UC UC UC UC UC UC UC 0 0 U C U C 0 0 1 1 Stall 0 1 1 Stall UUU C C C ignore UUU C C C ignore 0 1 1 Stall yes yes no no yes
Out endpoint Normal Out/erroneous In 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Out Out Out In <= 10 > 10 x x data junk junk UC valid x invalid x updates updates updates UC 1 updates 0 UC updates updates updates UC UC UC UC UC UC UC UC UC 1 1 1 UC 1 UC UC UC 1 0 0 0 ACK ignore ignore ignore yes yes yes no
NoChange NoChange NoChange
NAK Out/erroneous In 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Out Out Out In <= 10 > 10 x x UC UC UC UC valid x invalid x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC UC UC UC UC NoChange NoChange NoChange NoChange NAK ignore ignore ignore yes no no no
Isochronous endpoint (Out) 0 0 1 1 0 0 1 1 Out In x x updates UC updates x updates UC updates UC updates UC UC UC UC UC 1 UC 1 UC NoChange NoChange RX ignore yes no
In endpoint Normal In/erroneous Out 1 1 1 1 0 0 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 NoChange 1 ignore no yes
1 0 0 ACK (back)
NAK In/erroneous Out 1 1 1 1 0 0 0 0 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC UC NoChange NoChange ignore NAK no yes
Isochronous endpoint (In) 0 0 1 1 1 1 1 1 Out In x x UC UC x x UC UC UC UC UC UC UC UC UC 1 UC UC UC UC NoChange NoChange ignore TX no yes
17.0
Absolute Maximum Ratings
Storage Temperature ......................................................................................................................................... -65oC to +150oC Ambient Temperature with Power Applied .............................................................................................................. -0oC to +70oC Supply voltage on VCC relative to VSS .................................................................................................................. -0.5V to +7.0V DC input voltage .......................................................................................................................................... -0.5V to +VCC+0.5V DC voltage applied to outputs in High Z state............................................................................................. -0.5V to + VCC+0.5V Max. output current into Port 0,1,2,3 and DAC[1:0] pins...................................................................................................... 60 mA Max. output current into DAC[7:2] pins ............................................................................................................................... 10 mA Power dissipation ...............................................................................................................................................................300 mW Static discharge voltage .................................................................................................................................................... >2000V Latch-up current ............................................................................................................................................................. >200 mA
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18.0 DC Characteristics
Min 4.0 4.35 Max 5.5 5.25 40 15 20 10 0.4 256 128 1.024 14.33 1 60 Units V V mA mA A mA V s s ms ms A mA Conditions Non USB activity (note 1) USB activity (note 2) Vcc=5.5V Oscillator off, D- > Voh min Vcc = 5.0V (note 11) Vcc = 5.0V, ceramic resonator
Fosc = 6 MHz; Operating Temperature = 0 to 70C Parameter General Operating Voltage VCC (1) Operating Voltage VCC (2) Vcc Operating Supply Current ICC1 Vcc = 4.35 V ICC2 Supply Current - Suspend Mode ISB1 Supply Current - Start-up Mode ISB2 (12) Programming Voltage (disabled) VPP Resonator Start-up Interval Tstart Internal timer #1 interrupt period tint1 Internal timer #2 interrupt period tint2 WatchDog timer period twatch Input leakage current Iil Max Iss IO sink current Ism Power On Reset Vcc reset slew USB Interface Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage Bus Pull-up resistance Bus Pull-down resistance General Purpose I/O Interface Pull-up resistance Input threshold voltage Input hysteresis voltage Sink current Sink current Source current DAC Interface Pull-up resistance DAC[7:2] sink current (0) DAC[7:2] sink current (F) DAC[1:0] sink current (0) DAC[1:0] sink current (F) Programmed Isink ratio: max/min Differential nonlinearity Current sink response time Tracking ratio DAC[1:0] to DAC[7:2]
-0.4 128 1.024 8.192
any pin Cumulative across all ports (note 10)
tvccs Voh Vol Vdi Vcm Vse Cin Ilo Rpu Rpd Rup Vith VH Iol Iol Ioh Rup Isink0(0) Isink0(F) Isink1(0) Isink1(F) Irange Ilin tsink Tratio
0.01
200
ms
linear ramp: 0 to 4.35V (notes 4,5)
2.8 0.2 0.8 0.8 -10 7.35K 14.25
3.6 0.3 2.5 2.0 20 10 7.65 15.75
V V V V V pF s k k
15k 5% ohms to Gnd (notes 2,6) |(D+)-(D-)| 9-1
0 V < Vin<3.3 V 7.5 k 2% 15 k 5%
4.9K 45% 6% 7.2 3.5 1.4
9.1K 65% 12% 16.5 10.6 7.5
Ohms V CC VCC mA mA mA
All ports, low to high edge All ports, high to low edge Port 3, Vout = 1.0V (note 1) Port 0,1,2, Vout = 2.0V (note 1) Voh = 2.4V (all ports 0,1,2,3) (note 1)
8.0K 0.1 0.5 1.6 8 4
14
20.0K 0.3 1.5 4.8 24 6 0.5 0.8 20
Ohms mA mA mA mA lsb s
Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (note 2) Vout = 2.0 V DC (notes 2,12) any pin (note 7) Full scale transition Vout = 2.0V (note 9)
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19.0 Switching Characteristics
Description Clock tCYC tCH tCL tr tr tf tf trfm Vcrs tdrate tdjr1 tdjr2 tdeop teopr1 teopr2 teopt tudj1 tudj2 Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
.
Parameter
Min. 165.0 0.45 tCYC 0.45 tCYC 75
Max. 168.3
Unit ns ns ns ns
Conditions
Input clock cycle time Clock HIGH time Clock LOW time USB Driver Characteristics Transition Rise Time (notes 2,3,8) Transition Rise Time (notes 2,3,8) Transition Fall Time (notes 2,3,8) Transition Fall Time (notes 2,3,8) Rise/Fall Time Matching Output Signal Crossover Voltage USB Data Timing Low Speed Data Rate Receiver Data Jitter Tolerance Receiver Data Jitter Tolerance Differential to EOP transition Skew EOP Width at receiver EOP Width at receiver Source EOP Width Differential Driver Jitter Differential Driver Jitter
CLoad = 50 pF CLoad = 350 pF CLoad = 50 pF CLoad = 350 pF tr/tf (note 15)
300 75 300 80 1.3 1.4775 -75 -45 -40 165 675 1.25 -95 -150 1.50 95 150 120 2.0 1.5225 75 45 100
ns ns ns % V Mbs ns ns ns ns ns s ns ns
Ave. Bit Rate (1.5Mb/s 1.5%) To Next Transition, (note 13) For Paired Transitions, (note 13) (note 13) Rejects as EOP, (notes 13,14) Accepts as EOP, (note 13) To next transition, Figure 19-5 To paired transition, Figure 19-5
Functionality is guaranteed of this Vcc range, except USB transmitter, and DACs. USB transmitter functionality is guaranteed over this Vcc range, as well as DAC outputs. Per Table 7-6 of revision 1.0 of USB specification, for CLOAD of 50 - 350 pF. Port 3 bit 7 controls whether the parts goes into suspend after a POR event or waits 128ms to begin running. POR can occur only once per applied VCC, if VCC drops below Vrst, POR will not re-occur. VCC must return to 0.0V before POR will be re-applied on a subsequent VCC ramp. Vrst is nominally 1/2 Vcc but is not specified. Rx: external idle resistor, 7.5 K, 2%, to VCC. Measured as largest step size vs. nominal according to measured full scale and zero programmed values. This parameter is guaranteed, but not tested. Tratio = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed. Total current cumulative across all Port pins flowing to Vss is limited to minimize Ground-Drop noise effects. Tested under static conditions. Irange: Isinkn(15)/ Isinkn(0) for the same pin. Measured at cross-over point of differential data signals USB Specification indicates 330 ns. Tested at 200 pF.
tCYC tCH
CLOCK
tCL Figure 19-1. Clock Timing
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Voh Vcrs Vol
D+
tr
90% 10% 90%
tf
10%
D-
Figure 19-2. USB Data Signal Timing
TPERIOD Differential Data Lines
TJR TJR1 TJR2
Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + TJR2
Figure 19-3. Receiver Jitter Tolerance
TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width:
TEOPT
Receiver EOP Width: TEOPR1 , TEOPR2
Figure 19-4. Differential to EOP Transition Skew and EOP Width
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TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
Figure 19-5. Differential Data Jitter
20.0
Ordering Information
EPROM Size 4 KB 4 KB 6 KB 6 KB 8 KB 8 KB 8 KB 8 KB 4 KB 6 KB 8 KB 8 KB Package Name P17 O48 P17 O48 P17 O48 W18 W48 O48 O48 O48 W48 Package Type 40-Pin (600-Mil) PDIP 40-Pin (600-Mil) PDIP 40-Pin (600-Mil) PDIP 40-Pin (600-Mil) Windowed CerDIP 48-Pin Windowed SideBraze Operating Range Commercial Commercial Commercial Commercial Commercial
Ordering Code CY7C63411-PC CY7C63411-PVC CY7C63412-PC CY7C63412-PVC CY7C63413-PC CY7C63413-PVC CY7C63413-WC CY7C63413-WVC CY7C63511-PVC CY7C63512-PVC CY7C63513-PVC CY7C63513-WVC Document #: 38-00589-D
48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial
48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Pin Windowed SideBraze Commercial
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21.0 Package Diagrams
48-Lead Shrunk Small Outline Package O48
40-Lead (600-Mil) Molded DIP P17
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21.0 Package Diagrams (continued)
40-Lead (600-Mil) Windowed CerDIP W18
48-Lead (600-Mil) Windowed Sidebraze W48
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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